1. Field of the Invention
The present invention relates to a step-up booster circuit (the circuit is called “a step-up circuit” or “a booster circuit”), and more particularly to a step-up circuit which generates a step-up (boost) voltage to be supplied to a word line of a non-volatile semiconductor storage device.
2. Description of the Related Art
A non-volatile semiconductor storage device which can be electrically written and erased (an EEPROM) uses floating gate-type transistors as memory cells. Accordingly, in order to access a memory cell during reading of data from the memory cells or the like, a high voltage, which is higher than a power supply voltage, must be supplied to a word line connected to the memory cell. Step-up (booster) circuits which serve as circuits for generating these high voltages are available. An example of such step-up circuit is described in Japanese Patent Application Laid-Open (JP-A) No. 2005-339658.
In this reference, a charge-pump circuit is formed with one terminal of each of a plurality of capacitors being connected between respective transistors which structure a charge transfer circuit. A first clock signal generated by a clock generation circuit is supplied to the other terminal of each of the capacitors that are arranged at odd-number positions, and a second clock signal, which is opposite in phase to the first clock signal, is supplied to the other terminal of each of the capacitors that are arranged at even-number positions. As a result, sequential step-ups are implemented and a desired boost voltage is obtained.
In recent years, non-volatile semiconductor storage devices have been utilized in many electronic apparatuses. In a case in which, for example, a non-volatile semiconductor storage device is employed in a portable device which is operated by a battery, a reduction in power consumption of the non-volatile semiconductor storage device is sought. However, conventional step-up circuits, particularly step-up circuits which are employed in non-volatile semiconductor storage devices, have not had sufficient facility for reducing power consumption of the step-up circuits. Moreover, there are variations in thresholds Vtc of memory cells. If a range of such variations is Vtcx≧Vtc≧Vtcn (Vtcx being a maximum value of the memory cell threshold and Vtcn being a minimum value of the memory cell threshold), a word line voltage for times of reading must be set to a potential Vdd+Vtn which is equal to or greater than the maximum value Vtcx of the threshold of the memory cell. However, when memory cell data with the memory cell threshold minimum value Vtcn is being read with the above-mentioned potential Vdd+Vtn, there is an excess potential of Vdd+Vtn−Vtcn. Current consumption of a step-up circuit for producing this excess potential is large, which is a problem.